This project documents the reverse engineering and CPLD based recreation of the Compaq Deskpro Model 40 80386DX PC, preserving original system behavior using modern hardware.
There is a forum available on this website where regular development update articles will be published for interested visitors who want to follow the work. The articles provide historic design details and deeper insight into the process of preserving the technology by recreating it in modern forms. We will also do comparisons between the IBM 5170 and the Compaq Deskpro Model 40 to illustrate where they are identical and where they differ.
Project information and status
This website will be the primary source of information regarding the development process and progress updates. Which means all revisions will be described here in a continuous fashion as they evolve. So anyone interested in this project can check this page to follow my work. If you want to contact me or show your support in other ways, you can subscribe to my forum system here by email, just drop me a short message in the contact page and I will make a login for you to join the forum.
Designs from this project are strictly only for hobby and educational purposes, not for making any commercial profit. Offering boards specifically to retro hobby enthusiasts at cost prices is within the scope of intended use. It is not permitted to use these designs for any other purpose because the copyright of technology remains with HP and must be respected and observed. This project is strictly intended for historic preservation purposes. Only by rebuilding this historic system can we prove it to be functional and preserve it for the distant future, which is the primary purpose.
Initial project outline:
- transferring the original designs into KiCad
- analyzing and converting the PALASM logic into regular schematic or HDL representations
- designing a REV1 system using TTL/PAL logic, and a REV2 system using primarily CPLD logic.
Purpose and permitted use, cautions for a potential builder of this design
This project was created for historical purposes out of love for historical computing designs and for the purpose of enabling computing enthousiasts with a sufficient level of building and troubleshooting expertise to be able to experience the technology by building and troubleshooting the hardware described in this project. Due to the level of this project, it may be suitable as a project for students to get into. If there are any questions from teachers who like to teach about this technology I would be happy to answer them. It may be really interesting to analyse the elaborate and complex CPU timing and 8 bit to 16 bit data byte translation and DMA mechanisms in an educational setting.
This project is released under a GPL3 license and besides these license conditions there are a few additional warnings and usage restrictions applicable that any builder must read before proceeding with this project:
No guarantees of function or fitness for any particular or useful purpose are given, building and using this design is at the sole responsibility of the builder.
Do not attempt this project unless you have the necessary electronics assembly expertise and experience, and know how to observe all electronics safety guidelines which are applicable.
It is not permitted to use the computer built from this design without the assumption of the possibility of loss of data or malfunction of the connected device. To be used strictly for personal hobby and experimental purposes only. No applications are permitted where failure of the device could result in damage or injury of any kind.
If you plan to use this design or any part of it in new designs, the acknowledgement of the designer and the design sources and inspirations, historical and modern, of all subparts contained within this design should be included and respected in your publication, to accredit the hard work, time and effort dedicated by the people before you who contributed to make your project possible.
No guarantee for any proper operation or suitability for any possible use or purpose is given, using the resulting hardware from this design is purely educational and experimental and not intended for serious applications. Loss of data is likely and to be expected when connecting any storage device or storage media to the resulting system from this design, or when configuring or operating any storage device or media with the system of this design.
When connecting this system to a computer network which contains stored information on it, it is at the sole responsibility and risk of the person making the connection, no guarantee is given against data loss or data corruption, malfunctions or failure of the whole computer network and/or any information contained inside it on other devices and media which are connected to the same network.
When building this project, the builder assumes personal responsibility for troubleshooting it and using the necessary care and expertise to make it function properly as defined by the design. You can email me with questions, but I will reply only if I have time and if I find the question to be valid. Which will probably also lead to an update here. I want to primarily dedicate my time to new project development, I am not able to do any user support, so that’s why I provide the elaborate info here which will be expanded if needed.
Project development planning
This project aims to preserve the historic technology of the Compaq Deskpro Model 40 because it played a significant role in stimulating the direction of the PC industry standard. IBM wanted to move into proprietary technology in a standard which they controlled, it is unclear how this decision came about but it merits research. At the same time the other manufacturers in the PC industry moved to continue the standard from the ISA and PC/AT design path. Arguably the PC/AT represented a limiting factor on the 16 bit aspect however that is not really the important detail in the standard. The important point was that the PC industry moved forward, somehow. So the VESA Local Bus was created eventually which was a step forward. Further along the PCI standard was developed which was a further improvement, though increasingly complex to support.
So roughly the development planning is as follows:
- reproduce the design to prove and preserve the technology in a rebuild in the TTL/PAL REV1 stage
- reproduce the design to prove and preserve the technology in a rebuild in the CPLD REV2 stage
- further develop the system onward using the support of a FPGA chipset
REV1 and REV2 are currently under development and will evolve relatively simultaneously. Possibly for more flexible verification REV2 may be developed first so we can establish and test with various BIOS types.
The first two revisions have the primary purpose to verify and preserve the core Compaq technology. After that FPGA technology will be used to develop the system further, support larger amounts of modern types of RAM and possibly to enable more advanced resources to be connected with the 386DX CPU. For example PCI bus control and other technology is planned to be looked into.
Schematic entry and conversion stage are now in progress
At the moment I am working on creating a complete schematic of the Compaq Deskpro Model 40, when this work is completed I will share the initial schematic here and updates will follow.
A blog description and other details of the work will be shared in the project message thread, where you can see the project process in sequential steps as it develops.
Efforts have been made to contact original designer Paul R Culley who was involved in this system. If you are one of the original engineers or have additional information, please feel free to get in touch, it would be much appreciated!