Project to create the Turbo XT ATX Mainboard REV4
Posted: Thu Jul 30, 2026 3:57 pm
Project goals for this new XT PC mainboard design
After designing 3 revisions of XT mainboards, I am revisiting the XT system design, this time creating a completely new design where a few things will be fundamentally changed.
One thing will be that I will be using CPLD technology to speed up bus operations and create a much higher level of integration.
So I will remove a lot of the external logic of the previous XT designs and move the functions into CPLDs.
RAM and EMS
I am going to use 5 1MByte SRAM ICs to create the regular system RAM which also may support shadowing of the ROM code, and to create 4MByte of EMS RAM that is going to support the RealDOOM project. The functional structure will be identical to the REV3E EMS system. Sqpat is working on his SQEMM driver to be able to support among other things the Desqview multitasking application system. His work can be followed on his GitHub page for the EMS drivers.
New system control
I will create the design in such a way that the READY and bus control chips 8284 and 8288 will be able to be connected on an external removable module, where individual signals can be jumpered to connect or disconnect these with the mainboard. All the system control signals will be routed to the System controller CPLD as well, which will then be developed in incremental steps to fully replace the system control present in the bus controller ICs. At the end of the development process, we can remove the bus controller module completely from the system and use the integrated System controller to replace all their functions.
AT slot control
16 bit AT slots are used in the design. In this design I am thinking about using custom logic to interface with various signals and functions of the 16 bit slot extension part. This may include experiments with the high data bus on the slot and system data bus, and using /IO_CS_16 and /MEM_CS_16 as decoding signals to drive the 16 bit data bus conversion cycles. Possibly we could use SA0 to decode the byte steering to the 8 bit CPU for normal byte operations, and for byte conversion we could experiment with system control to provide a reverse byte conversion from a 16 bit bus to an 8 bit CPU instead of from an 8 bit bus to a 16 bit CPU. Possibly the 5170 PC/AT system control logic could be modified to extend wait state timing and do the reverse conversion and latching between 8 and 16 bit operations.
Possibly in our system we could use byte steering and latching to simulate the same or similar but compatible mechanism for different types of operations as done in the XT-IDE hardware design. Since this involves the IDE operation, possibly a larger IO decoder CPLD could be dual purposed to support 16 to 8 bit conversions, at least for IDE control. XT-IDE BIOS and hardware ideas were developed by the XT-IDE Universal BIOS team. There are more details listed on the Glitchworks GitHub page which also includes the people involved in developing the XT-IDE interface. Thanks go out to Scott Christensen, Jeff Leyda/Hargle and Andrew Lynch/N8VEM for their work to create the XT-IDE hardware ideas and getting these known among retro enthusiast builders and developers. Which includes this project as well. Thanks to everyone involved! I am not clear on what is the latest XT-IDE hardware design, or exactly what constitutes the current design standard. I used the XT-IDE interface in several XT mainboard designs, and this time I will likely feature it completely inside the IO Decoder CPLD. Since there may be delays involved I will need to look into some kind of delay mechanisms possibly using fast clock signals. More about this will follow later when more design details are worked out.
VGA controller
For VGA in this and other projects, the Cirrus Logic GD5434 is advised. In ISA bus mode, this controller is able to run in 8 bit compatibility mode so no form of byte conversion is needed for VGA operations, the VGA controller handles the byte control with VGA RAM cycles internally. In addition, the VGA BIOS ROM can be integrated in the system ROM when using this card, so no ROM would be needed on the VGA card design for this controller which simplifies the ISA card design.
Core AT controllers
So we will feature these Core AT controllers:
2x 8259 Interrupt controller (second interrupt controller is pending a suitable BIOS can be found to support it)
8253 system timer
one 8237 DMA controller (we only need the sound and floppy drive DMA channels)
8255 PPI based XT keyboard control, using a CPLD to provide the interface between the keyboard and the 8255 port.
DS12885 RTC containing CMOS configuration memory
DMA page mapper: we will use the standard 74LS670 part from the PC/XT design.
The second interrupt controller would be useful especially to support VGA cards which use interrupts in the 16 bit slot section.
USB to serial mouse
For this project we will use the excellent USB to serial mouse conversion system based on a RP2040, created by LimeProgramming on GitHub. The mouse support can use a modern mouse receiver and provides comfortable mouse control identical to any modern PC with a USB mouse.
Space and CPLD pins permitting we may add more interfaces supported by a RP2040 to the system.
Clock speed
After migrating system control into the system controller CPLD, we will look into supporting much higher clock speeds in the system.
For example around 20MHz if the CPU in question supports this.
It's unsure how this would require BIOS support regarding timing routines but possibly existing more modern BIOS types may support adjusting to a higher clock oscillator speed.
CPU types
The type of supported CPU is still being researched and I will discuss this with other people interested in this project. Possibly different socket types may be included in the board design where a builder for example can easily insert a PLCC package CPU into the board socket. Possibly the PLCC chip types would be typically more modern and support higher clock speeds by using more modern CMOS technology.
Project status
I am working on the system schematic by merging design areas from different projects.
After that I will assemble quartus projects and distribute the system bus and functions between different CPLDs.
Being an 8 bit system it may provides a distinct advantage when using CPLDs because we don't have a double byte data steering which requires separate byte controls. We will have to find out how this pans out in the system distribution and OE equation requirements.
Kind regards,
Rodney
If you like to join feel welcome to get in touch with me!
After designing 3 revisions of XT mainboards, I am revisiting the XT system design, this time creating a completely new design where a few things will be fundamentally changed.
One thing will be that I will be using CPLD technology to speed up bus operations and create a much higher level of integration.
So I will remove a lot of the external logic of the previous XT designs and move the functions into CPLDs.
RAM and EMS
I am going to use 5 1MByte SRAM ICs to create the regular system RAM which also may support shadowing of the ROM code, and to create 4MByte of EMS RAM that is going to support the RealDOOM project. The functional structure will be identical to the REV3E EMS system. Sqpat is working on his SQEMM driver to be able to support among other things the Desqview multitasking application system. His work can be followed on his GitHub page for the EMS drivers.
New system control
I will create the design in such a way that the READY and bus control chips 8284 and 8288 will be able to be connected on an external removable module, where individual signals can be jumpered to connect or disconnect these with the mainboard. All the system control signals will be routed to the System controller CPLD as well, which will then be developed in incremental steps to fully replace the system control present in the bus controller ICs. At the end of the development process, we can remove the bus controller module completely from the system and use the integrated System controller to replace all their functions.
AT slot control
16 bit AT slots are used in the design. In this design I am thinking about using custom logic to interface with various signals and functions of the 16 bit slot extension part. This may include experiments with the high data bus on the slot and system data bus, and using /IO_CS_16 and /MEM_CS_16 as decoding signals to drive the 16 bit data bus conversion cycles. Possibly we could use SA0 to decode the byte steering to the 8 bit CPU for normal byte operations, and for byte conversion we could experiment with system control to provide a reverse byte conversion from a 16 bit bus to an 8 bit CPU instead of from an 8 bit bus to a 16 bit CPU. Possibly the 5170 PC/AT system control logic could be modified to extend wait state timing and do the reverse conversion and latching between 8 and 16 bit operations.
Possibly in our system we could use byte steering and latching to simulate the same or similar but compatible mechanism for different types of operations as done in the XT-IDE hardware design. Since this involves the IDE operation, possibly a larger IO decoder CPLD could be dual purposed to support 16 to 8 bit conversions, at least for IDE control. XT-IDE BIOS and hardware ideas were developed by the XT-IDE Universal BIOS team. There are more details listed on the Glitchworks GitHub page which also includes the people involved in developing the XT-IDE interface. Thanks go out to Scott Christensen, Jeff Leyda/Hargle and Andrew Lynch/N8VEM for their work to create the XT-IDE hardware ideas and getting these known among retro enthusiast builders and developers. Which includes this project as well. Thanks to everyone involved! I am not clear on what is the latest XT-IDE hardware design, or exactly what constitutes the current design standard. I used the XT-IDE interface in several XT mainboard designs, and this time I will likely feature it completely inside the IO Decoder CPLD. Since there may be delays involved I will need to look into some kind of delay mechanisms possibly using fast clock signals. More about this will follow later when more design details are worked out.
VGA controller
For VGA in this and other projects, the Cirrus Logic GD5434 is advised. In ISA bus mode, this controller is able to run in 8 bit compatibility mode so no form of byte conversion is needed for VGA operations, the VGA controller handles the byte control with VGA RAM cycles internally. In addition, the VGA BIOS ROM can be integrated in the system ROM when using this card, so no ROM would be needed on the VGA card design for this controller which simplifies the ISA card design.
Core AT controllers
So we will feature these Core AT controllers:
2x 8259 Interrupt controller (second interrupt controller is pending a suitable BIOS can be found to support it)
8253 system timer
one 8237 DMA controller (we only need the sound and floppy drive DMA channels)
8255 PPI based XT keyboard control, using a CPLD to provide the interface between the keyboard and the 8255 port.
DS12885 RTC containing CMOS configuration memory
DMA page mapper: we will use the standard 74LS670 part from the PC/XT design.
The second interrupt controller would be useful especially to support VGA cards which use interrupts in the 16 bit slot section.
USB to serial mouse
For this project we will use the excellent USB to serial mouse conversion system based on a RP2040, created by LimeProgramming on GitHub. The mouse support can use a modern mouse receiver and provides comfortable mouse control identical to any modern PC with a USB mouse.
Space and CPLD pins permitting we may add more interfaces supported by a RP2040 to the system.
Clock speed
After migrating system control into the system controller CPLD, we will look into supporting much higher clock speeds in the system.
For example around 20MHz if the CPU in question supports this.
It's unsure how this would require BIOS support regarding timing routines but possibly existing more modern BIOS types may support adjusting to a higher clock oscillator speed.
CPU types
The type of supported CPU is still being researched and I will discuss this with other people interested in this project. Possibly different socket types may be included in the board design where a builder for example can easily insert a PLCC package CPU into the board socket. Possibly the PLCC chip types would be typically more modern and support higher clock speeds by using more modern CMOS technology.
Project status
I am working on the system schematic by merging design areas from different projects.
After that I will assemble quartus projects and distribute the system bus and functions between different CPLDs.
Being an 8 bit system it may provides a distinct advantage when using CPLDs because we don't have a double byte data steering which requires separate byte controls. We will have to find out how this pans out in the system distribution and OE equation requirements.
Kind regards,
Rodney
If you like to join feel welcome to get in touch with me!