Historic computer technology preservation

I have checked all the voltages on the REV4 QFP mainboard to be correct.
I then proceeded to solder the FPGA, serial flash configuration ROM, bus switch ICs, SRAMs, 286 CPU socket and system ROM socket strips.

After all the SMD ICs in the core FPGA/CPU area were in place and checked to be solid on ...

After doing a lot of soldering on the REV4 QFP mainboard, I want to document the process of building the REV4 QFP system here.
I more in depth description of my process can provide a builder with a few guidelines regarding the order of assembling and testing the mainboard.

So I first soldered all ...

I have previously done some testing on the REV3E system and this led me to believe that this system may be capable of running at higher clock speeds.

Since we now have a System controller CPLD design which is fully synchronous by using double the 286_CLK clock frequency on the CPLD clock input ...

So after my recent findings to further improve the PC/AT system controller derived from the original IBM 5170 technology, I am currently looking into a follow up REV2C system design. Since the completely revised system controller design is also applicable in the PLCC/TTL based design iteration, this ...

Okay so looking at the PC/AT system in general, inside the system controller there are a lot of logic areas. In order to support the entire system control I created a state machine that follows the 80286 cycles and from the state machine we can decode where the 80286 is operating in the sequence of ...

After getting the 8 bit mode ROM functioning on the REV2C system, I decided to prepare the system for the new system controller CPLD programming.

A few things are moved into the System controller so now we can get rid of U89 entirely.
We will generate all the DMA commands directly from the System ...

So after making so much progress developing the REV3E System controller CPLD to now function almost completely on synchronous logic, I decided to revisit the REV2A modified system using TTL and PLCC CPLDs. I now want to see what I can do with this system after all the findings with the REV3E system ...

Okay, now I am making huge progress on the REV3E System controller, I have some very exciting news!

Today I was able to achieve something that was previously not possible.
I have created hundreds of quartus design projects in the past period, however up to today it has been illusive to be able to ...

I have done a lot more development on the System control design of the REV3E stage.

I started with merging the PCLOCK and SYS_CLK clock signals.
Previously I was not able to do this in a stable way, however this time I attempted again and finally succeeded to accomplish this.
So now the whole ...

This is my latest resulting project as verified on 14-8-2026.
Check the link to the file on GitHub below for the ZIP archive download.

I have developed the REV3E 80286 System controller CPLD design further which now includes synchronously created timing and control signals in even more of the ...